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AMP374P6453BT1-C1H/S
64M X 72 SDRAM DIMM with ECC based on 32M X 8, 4 Banks, 8K REFRESH, 3.3V Synchronous DRAMs WITH SPD
DESCRIPTION AVED Memory Products AMP374P6453BT1-C1H/S is a 64M bit X 72 Synchronous Dynamic RAM high density memory module. The AVED Memory Products AMP374P6453BT1-C1H/S consists of eighteen CMOS 32M X 8 bit with 4 banks Synchronous DRAMs in TSOP-II 400mil package and a 2K EEPROM in 8-pin TSSOP package on a 168-pin glass-epoxy substrate. Two 0.1uF decoupling capacitors are mounted on the printed circuit board in parallel for each SDRAM. The AVED Memory Products AMP374P6453BT1-C1H/S is a Dual In-Line Memory Module and is intended for mounting into 168-pin edge connector sockets. Synchronous design allows precise cycle control with the use of system clock. I/O transactions are possible on every clock cycle. Range of operating frequencies, programmable latencies allows the same device to be useful for a variety of high bandwidth, high performance memory system applications. APPLICATION Main Memory unit for computer, Microcomputer memory, Refresh memory for CRT. FEATURES * Performance Ranges * Part Identification - AMP374P6453BT1-C1H/S 8k cycles/64ms Ref, TSOP, Gold Contact Plating - PC100 Compliant
PIN NAMES
P in N a m e A0 - A12 BA0 - BA1 DQ0 - DQ63 CB0 - 7 CLK0 - CLK3 CKE0 - CKE1 CS0 - CS3 RAS CAS WE DQM0 - 7 VDD V ss *V R E F SDA SCL SA0 - 2 WP DU NC F u n c tio n A d d re ss In p u t (m u ltip le xe d ) S e le ct B a n k D a ta In p u t/O u tp u t C h e ck B it (D a ta -in /o u t) C lo ck In p u t C lo ck E n a b le In p u t C h ip S e le ct In p u t R o w A d d re ss S tro b e C o lu m n A d d re ss S tro b e W rite E n a b le DQM P o w e r S u p p ly (3 .3 V ) G ro u n d P o w e r S u p p ly fo r R e fe re n ce S e ria l A d d re ss D a ta I/O S e ria l C lo ck A d d re ss in E E P R O M W rite P ro te ct D o n 't U se N o C o n n e ctio n
Part # Maximum Frequency/Speed AMP374P6453BT1-C1H/S PC100MHz (10ns @ CL=2) * * * * * Burst Mode Operation Auto & Self Refresh capability (8k cycles/64ms) LVTTL compatible inputs and outputs Single 3.3V 0.3V power supply MRS cycle with address key programs Latency (Access from column address) Burst Length (1, 2, 4, 8 & Full Page) Data Scramble (Sequential & Interleave) * All inputs are sampled at the positive going edge of the system clock
* Serial Presence Detect with EEPROM
Revision: 1.1
Revision Date: 11/2000
Document Number: 65830
Page Number: 1 of 12
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AMP374P6453BT1-C1H/S
64M X 72 SDRAM DIMM with ECC based on 32M X 8, 4 Banks, 8K REFRESH, 3.3V Synchronous DRAMs WITH SPD
PIN CONFIGURATIONS (FRONT SIDE / BACK SIDE) Pin
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28
Front
Vss DQ0 DQ1 DQ2 DQ3 VDD DQ4 DQ5 DQ6 DQ7 DQ8 Vss DQ9 DQ10 DQ11 DQ12 DQ13 VDD DQ14 DQ15 CB0 CB1 Vss NC NC VDD
WE
Pin
29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56
Front
DQM1
CS0
Pin
57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84
Front
DQ18 DQ19 VDD DQ20 NC *VREF CKE1 Vss DQ21 DQ22 DQ23 Vss DQ24 DQ25 DQ26 DQ27 VDD DQ28 DQ29 DQ30 DQ31 Vss CLK2 NC WP **SDA **SCL VDD
Pin
85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112
Back
Vss DQ32 DQ33 DQ34 DQ35 VDD DQ36 DQ37 DQ38 DQ39 DQ40 Vss DQ41 DQ42 DQ43 DQ44 DQ45 VDD DQ46 DQ47 CB4 CB5 Vss NC NC VDD
CAS
Pin
113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140
Back
DQM5
CS1 RAS
Pin
141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168
Back
DQ50 DQ51 VDD DQ52 NC *VREF NC Vss DQ53 DQ54 DQ55 Vss DQ56 DQ57 DQ58 DQ59 VDD DQ60 DQ61 DQ62 DQ63 Vss CLK3 NC **SA0 **SA1 **SA2 VDD
DU Vss A0 A2 A4 A6 A8 A10/AP BA1 VDD VDD CLK0 Vss DU
CS2
Vss A1 A3 A5 A7 A9 BA0 A11 VDD CLK1 A12 Vss CKE0
CS3
DQM0
DQM2 DQM3 DU VDD NC NC CB2 CB3 Vss DQ16 DQ17
DQM4
DQM6 DQM7 *A13 VDD NC NC CB6 CB7 Vss DQ48 DQ49
Pins marked * are not used in this module. Pins marked ** should be NC in the system which does not support SPD.
Revision: 1.1
Revision Date: 11/2000
Document Number: 65830
Page Number: 2 of 12
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AMP374P6453BT1-C1H/S
64M X 72 SDRAM DIMM with ECC based on 32M X 8, 4 Banks, 8K REFRESH, 3.3V Synchronous DRAMs WITH SPD
PIN CONFIGURATION DESCRIPTION
Pin
CLK CS CKE
Name
System Clock Chip Select Clock Enable
Input Function
Active on the positive going edge to sam ple all inputs. Disables or enables device operation by masking or enabling all inputs except CLK, CKE, and DQM. Masks system clock to freeze operation from the next clock cycle. CKE should be enabled at least one cycle prior to new comm and. Disable input buffers for power down in standby. CKE should be enabled 1CLK+t ss prior to valid com mand. Row/Column addresses are m ultiplexed on the sam e pins. Row Address: RA0 - RA12, Column address: CA0 - CA9 Selects bank to be activated during row address latch tim e. Selects bank for read/write during column address latch tim e. Latches row addresses on the positive going edge of the CLK with RAS low. Enables row access & precharge.
A0 - A12
Address
BA0 - BA1
Bank Select Address
RAS
Row Address Strobe
CAS
Colum n Address Strobe
Latches column addresses on the positive going edge of the CLK with C A S low. Enables colum n access. Enables write operation and row precharge. Latches data in starting from CAS , WE active.
WE
W rite Enable
DQM0 - DQM7 DQ0 - DQ63 CB0 - 7
Data Input/Output Mask Data Input/Output Check bit
Makes data output Hi-Z, tSHZ after the clock and masks the output. Blocks data input when DQM active. (Byte Masking) Data inputs/outputs are m ultiplexed on the same pins. Check bits for ECC.
WP
W rite Protect
VDD/Vss
Power Supply/Ground
W P pin is connected to Vss through 47K Resistor. W hen W P is "high" EEPROM program ming will be inhibited, and the entire m em ory will be write-protected. Power and ground for the input buffers and the core logic.
Revision: 1.1
Revision Date: 11/2000
Document Number: 65830
Page Number: 3 of 12
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AMP374P6453BT1-C1H/S
64M X 72 SDRAM DIMM with ECC based on 32M X 8, 4 Banks, 8K REFRESH, 3.3V Synchronous DRAMs WITH SPD
ABSOLUTE MAXIMUM RATINGS Item
Voltage on any pin relative to Vss Voltage on VDD supply relative to Vss Storage Temperature Power Dissipation Short Circuit Current
Symbol
VIN, VOUT VDD, VDDQ Tstg Pd IOS
Rating
-1.0 - 4.6 -1.0 - 4.6 -55 to + 150 18 50
Unit
V V C W mA
Note: Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded. Functional operation should be restricted to the conditions as detailed in the operational sections of this data sheet. Exposure to higher than recommended voltage for extended periods may affect device reliability.
DC OPERATING CONDITIONS AND CHARACTERISTICS Recommended operating conditions
(Voltage referenced to Vss=OV, Ta = 0 to 70C)
Item
Supply voltage Input logic high voltage Input logic low voltage Output logic high voltage Output logic low voltage Input leakage current (Inputs)
Symbol
VDD, VDDQ VIH VIL VOH VOL ILI
Min
3.0 2.0 -0.3 2.4 -10
Typ
3.3 3.0 0 -
Max
3.6 VDDQ+0.3 0.8 0.4 10
Unit
V V V V V A
Notes
1 2 IOH = -2mA IOL = 2mA 3
Note:1. 2. 3.
VIH(max) = 5.6V AC. Pulse width3ns. VIL(min) = -2.0V AC. Pulse width3ns Any input 0V VIN VDDQ. Input leakage currents include Hi-Z output leakage for all bi-directional buffers with Tri-State outputs.
CAPACITANCE (VDD = 3.3V, Ta = 23C, f=1MHz, VREF = 1.4V 200mV) Item
Input capacitance [A0 - A12, BA0 - BA1] Input capacitance [ RAS , CAS , WE ] Input capacitance [CKE0 - CKE1] Input capacitance [CLK0 - CLK3] Input capacitance [CS0 - CS3] Input capacitance [DQM0 - DQM7] Data input/output capacitance[DQ0 - DQ63] Check bit [CB0 - 7]
Symbol
CADD CIN CCKE CCLK CCS CDQM COUT1 COUT2
Min
50 50 28 18 18 13 13 13
Max
95 95 50 25 30 20 18 18
Unit
pF pF pF pF pF pF pF pF
Revision: 1.1
Revision Date: 11/2000
Document Number: 65830
Page Number: 4 of 12
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AMP374P6453BT1-C1H/S
64M X 72 SDRAM DIMM with ECC based on 32M X 8, 4 Banks, 8K REFRESH, 3.3V Synchronous DRAMs WITH SPD
DC AND OPERATING CHARACTERISTICS (Recommended operating conditions unless otherwise noted) T A = 0 to 70C Symbol
ICC1*
Test Condition
Burst Length = 1 tRC tRC (min) IOL = 0mA CKE VIL (max), tCC = 10ns CKE & CLK VIL (max), tCC = CKE VIH (min), CS VIH (min), tCC = 10ns Input signals are changed one time during 20ns CKE VIH (min), CLK VIL (max), tCC = Input signals are stable CKE VIL (max), tCC = 10ns CKE & CLK VIL(max), tCC = CKE VIH(min), CS VIH(min), tCC = 10ns Input signals are changed one time during 20ns CKE VIH(min), CLK VIL(max), tCC = Input signals are stable IOL = 0mA Page Burst 4 Banks activated tCCD = 2CLKS tRC tRC (min) CKE 0.2V
Version -1H
1,260 36 36 288 252 108 108 540 450
Unit
mA mA
ICC2P ICC2PS ICC2N ICC2NS ICC3P ICC3PS ICC3N ICC3NS ICC4
mA
mA
mA
mA 1,305
ICC5 ICC6
2,070 90
mA mA
ICC1: ICC2P: ICC2PS: ICC2N: ICC2NS: ICC3P: ICC3PS: ICC3N: ICC3NS: ICC4: ICC5 ICC6:
Notes:
Operating Current (one bank active) Precharge Standby Current in power-down mode Precharge Standby Current in power-down mode. Precharge Standby Current in non power-down mode. Precharge Standby Current in non power-down mode. Active Standby Current in power-down mode. Active Standby Current in power-down mode. Active Standby Current in non power-down mode (One Bank Active). Active Standby Current in non power-down mode (One Bank Active). Operating Current (Burst Mode) Refresh Current Self Refresh Current
1. Measured with outputs open. 2. Refresh period is 64ms. 3. Unless otherwise noted, input swing level is CMOS(VIH/VIL=VDDQ/VSSQ).
Revision: 1.1
Revision Date: 11/2000
Document Number: 65830
Page Number: 5 of 12
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AMP374P6453BT1-C1H/S
64M X 72 SDRAM DIMM with ECC based on 32M X 8, 4 Banks, 8K REFRESH, 3.3V Synchronous DRAMs WITH SPD
AC OPERATING TEST CONDITIONS ( VDD = 3.3V 0.3V, TA = 0 to 70C) Parameter
AC input levels Input timing measurement reference level Input rise and fall time Output measurement reference level Output load condition
Value
VIH/VIL= 2.4V / 0.4V 1.4V tr / tf = 1ns / 1ns 1.4V See Fig. 2
OPERATING AC PARAMETER (AC operating conditions unless otherwise noted) Refer to the individual component not the whole module. Parameter
Row active to row active delay RAS to CAS delay Row precharge time Row active time Row cycle time Last data in to row precharge Last data in to active delay Last data in to new col. add. delay Last data in to burst stop Column address to col. add. delay Number of valid output data
Symbol
tRRD (min) tRCD (min) tRP (min) tRAS (min) tRAS (max) tRC (min) tRDL (min) tDAL (min) tCDL (min) tBDL (min) tCCD (min) CAS latency = 2
Version
-1H 20 20 20 50 100 70 2 2CLK + 20 ns 1 1 1 1
Unit
ns ns ns ns us ns CLK CLK CLK CLK ea
Note
1 1 1 1 1 2,5 5 2 2 3 4
Note : 1. 2. 3. 4. 5.
The minimum number of clock cycles is determined by dividing the minimum time required with clock cycle time, and then rounding off to the next higher integer. Minimum delay is required to complete write. All parts allow every cycle column address change. In case of row precharge interrupt, auto precharge and read burst stop. For -80/1H/1L, tRDL=1CLK and tDAL=1CLK+20ns is also supported.
Revision: 1.1
Revision Date: 11/2000
Document Number: 65830
Page Number: 6 of 12
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AMP374P6453BT1-C1H/S
64M X 72 SDRAM DIMM with ECC based on 32M X 8, 4 Banks, 8K REFRESH, 3.3V Synchronous DRAMs WITH SPD
AC CHARACTERISTICS (AC Operating conditions unless otherwise noted) Refer to the individual component, not the whole module.
Parameter CLK cycle time CLK to valid output delay Output data hold time CLK high pulse width CLK low pulse width Input setup time Input hold time CLK to output in Low-Z CLK to output in Hi-Z
Symbol tCC tSAC tOH tCH tCL tSS tSH tSLZ tSHZ Min 10 3 3 3 2 1 1
-1H
Unit Max 1000 6 6 ns ns ns ns ns ns ns ns ns
Note 1 1,2 2 3 3 3 3 2
Note:
1. 2. 3.
Parameters depend on programmed CAS latency. If clock rising time is no longer than 1ns, (tr/2-0.5)ns should be added to the parameter. Assumed input rise and fall time (tr & tf) = 1ns. If tr & tf is longer than 1ns, transient time compensation should be considered, i.e., [(tr + tf)/2 - 1] ns should be added to the parameter.
Revision: 1.1
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Document Number: 65830
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AMP374P6453BT1-C1H/S
64M X 72 SDRAM DIMM with ECC based on 32M X 8, 4 Banks, 8K REFRESH, 3.3V Synchronous DRAMs WITH SPD
SIMPLIFIED TRUTH TABLE COMMAND
Register Refresh Mode Register Set Auto Refresh Self Entry Refresh Exit
CKEn-1 CKEn CS RAS CAS WE DQM B0,1 A10/AP A12-11,A9-0 Note
H H L
X H L H X X
L L L H L L
L L H X L H
L L H X H L
L H H X H H
X X X X X V V
OP CODE X X Row Address L Column H Address
(A0-A9)
1, 2 3 3 3 3 4 4, 5 4 4, 5 6 X
Bank Active & Row Address H Read & Auto Precharge Disable Column Address Auto Precharge Enable H Write & Auto Precharge Disable Column Address Auto Precharge Enable H Burst Stop Precharge Clock Suspend or Active Power Down H H H L H L H H
X X X L H L H
L L L H L X H L H L H L
H H L X V X X H X V X X H
L H H X V X X H X V X H
L L L X V X X H X V X H
X X X X
V
L H X L H X
Column Address (A0-A9)
Bank Selection All Banks Entry Exit
V X
Precharge Power Down Mode
Entry Exit
X X X X V X X X 7
DQM No Operation Command
X
(V = Valid, X = Don't Care, H = Logic High, L = Logic Low) Note: 1. 2. 3. OP Code: Operand Code A0 - A12, BA0 - BA1: Program keys. (@MRS) MRS can be issued only at all banks precharge state. A new command can be issued after 2 clock cycles of MRS. Auto refresh functions are same as CBR refresh of DRAM. The automatic precharge without row precharge command is meant by "Auto". Auto/self refresh can be issued only at all banks precharge state. BA0 - BA1: Bank select addresses. If both BA0 and BA1 are "Low" at read, write, row active and precharge, bank A is selected. If both BA0 is "Low" and BA1 is "High" at read, write, row active and precharge, bank B is selected. If both BA0 is "High" and BA1 is "Low" at read, write, row active and precharge, bank C is selected. If both BA0 and BA1 are "High" at read, write, row active and precharge, bank D is selected. If A10/AP is "High" at row precharge, BA0 and BA1 are ignored and all banks are selected. During burst read or write with auto precharge, new read/write command can not be issued. Another bank read/write command can be issued after the end of burst. New row active of the associated bank can be issued at tRP after the end of burst. Burst stop command is valid at every burst length. DQM sampled at positive going edge of a CLK masks the data-in at the very CLK (Write DQM latency is 0) but makes Hi-Z state the data-out of 2 CLK cycles after. (Read DQM latency is 2)
4.
5.
6. 7.
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AMP374P6453BT1-C1H/S
64M X 72 SDRAM DIMM with ECC based on 32M X 8, 4 Banks, 8K REFRESH, 3.3V Synchronous DRAMs WITH SPD
FUNCTIONAL BLOCK DIAGRAM
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AMP374P6453BT1-C1H/S
64M X 72 SDRAM DIMM with ECC based on 32M X 8, 4 Banks, 8K REFRESH, 3.3V Synchronous DRAMs WITH SPD
PACKAGE DIMENSIONS
Units: Inches(Millimeters)
Tolerances: .005(.13) unless otherwise specified
AVED Memory Products reserves the right to change products and specifications without notice
Revision: 1.1
1.2
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AMP374P6453BT1-C1H/S
64M X 72 SDRAM DIMM with ECC based on 32M X 8, 4 Banks, 8K REFRESH, 3.3V Synchronous DRAMs WITH SPD
SERIAL PRESENCE DETECT
* * * * * Organization: 64M x 72 Composition: 32M x 8*18 # of rows in module: 2 # of banks in component: 4 Refresh: 8K/64ms
Byte# 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 Function Description # of bytes written into serial memory at module manufacturer Total # of bytes of SPD memory devices Fundamental memory type # of row address on this assembly # of column address on this assembly # of module rows on this assembly Data width of this assembly Data width of this assembly Voltage interface standard of this assembly SDRAM cycle time @ CAS latency 3 SDRAM access time from clock @ CAS latency 3 DIMM configuration type Refresh rate and type Primary SDRAM width Error checking SDRAM width Minimum clock delay for back-to-back random column address SDRAM device attributes: Burst lengths supported SDRAM device attributes: # of banks on SDRAM device SDRAM device attributes: CAS latency SDRAM device attributes: CS latency SDRAM device attributes: Write latency SDRAM module attributes Function Supported -1H 128 bytes 256 bytes (2K-bit) SDRAM 13 10 2 72 bits LVTTL 10ns 6ns ECC 7.8 s, support self refresh x8 x8 tCCD = 1CLK 1,2,4,8 & Full page 4 banks 2&3 0 CLK 0 CLK Non-buffered, Nonregistered & redundant addressing 10% voltage tolerance, Burst read, Single bit Write, precharge all, auto precharge 10ns 6ns 20ns 20ns 20ns 50ns 2 rows of 256MB 2ns 1ns 2ns 1ns Hex Value -1H 80h 08h 04h 0Dh 0Ah 02h 48h 00h 01h A0h 60h 02h 82h 08h 08h 01h 8Fh 04h 06h 01h 01h 00h Note
1 1
2 2
22
SDRAM device attributes: General
OEh
23 24 25 26 27 28 29 30 31 32 33 34 35 36-61
SDRAM cycle time @ CAS latency 2 SDRAM access time from clock @ CAS latency 2 SDRAM cycle time @ CAS latency 1 SDRAM access time from clock @ CAS latency 1 Minimum row precharge time (=tRP) Minimum row active to row active delay(tRRD) Minimum RAS to CAS delay (=tRCD) Minimum activate precharge time(=tRAS) Module row density Command and address signal input setup time Command and address signal input hold time Data signal input setup time Data signal input hold time Superset information (may be used in the future)
A0h 60h 00h 00h 14h 14h 14h 32h 40h 20h 10h 20h 10h 00h
2 2
Revision: 1.1
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Document Number: 65830
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AMP374P6453BT1-C1H/S
64M X 72 SDRAM DIMM with ECC based on 32M X 8, 4 Banks, 8K REFRESH, 3.3V Synchronous DRAMs WITH SPD
SERIAL PRESENCE DETECT
(CONTINUED FROM PRESIOUS PAGE)
Byte# 62 63 64 65-71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100-103 104-130 131 132 133+
Function Description SPD data revision code Check sum for bytes 0-62 Manufacturer JEDEC ID code Manufacturer JEDEC ID code Manufacturing location Manufacturer part # Manufacturer part # Manufacturer part # Manufacturer part # Manufacturer part # Manufacturer part # Manufacturer part # Manufacturer part # Manufacturer part # Manufacturer part # Manufacturer part # Manufacturer part # Manufacturer part # Manufacturer part # Manufacturer part # Manufacturer part # Manufacturer part # Manufacturer part # Manufacturer revision code (for PCB) Manufacturer revision code (for component) Manufacturer part # Manufacturer part # Manufacturer part # Manufacturer revision code (for PCB) Manufacturer revision code (for component) Manufacturing date (Week) Manufacturing date (Year) Assembly serial # Manufacturer specific data (for future use) System frequency for 100MHz PC100 specification details Unused storage locations
Function Supported -1H PC100 SPD Spec. Ver. 1.2A AVED Memory Products AVED Memory Products Tustin A M P 3 7 4 P 6 4 5 3 B T 1 "-" C 1 H / S 1 H 0 B-die (3RD Gen.) Undefined 100MHz Detailed 100MHz information Undefined
Hex Value -1H 12h 4Ch 67h 00h 01h 41h 4Dh 50h 33h 37h 34h 50h 36h 34h 35h 33h 42h 54h 31h 2Dh 43h 31h 48h 2Fh 53h 31h 48h 20h 30h 42h 64h FFh -
Note
3 3 4 5
5
Notes: 1. The bank select address is excluded in counting the total # of Addresses. 2. This value is based on the component specification. 3. These bytes are programmed by code of Date, Week & Date, Year with BCD format. 4. These bytes are programmed by AVED's own assembly serial # system. All modules may have different unique serial #s. 5. These bytes are Undefined and can be used for AVED's own purpose.
Revision: 1.1
Revision Date: 11/2000
Document Number: 65830
Page Number: 12 of 12

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